The seL4 microkernel


  1. Revision history for seL4
  2. For more information see the release notes at
  3. This file should be word wrapped to 120 characters
  4. The upcoming release notes should indicate whether it is a SOURCE COMPATIBLE, BINARY COMPATIBLE or BREAKING change. As
  5. changes are added the compatibility information should be updated.
  6. ---
  7. Upcoming release: BREAKING
  8. ## Changes
  9. * Add GrantReply access right for endpoint capabilities.
  10. - seL4_Call is permitted on endpoints with either the Grant or the GrantReply access rights.
  11. - Capabilities can only be transferred in a reply message if receiver's endpoint capability has the Grant right.
  12. * `seL4_CapRights_new` now takes 4 parameters
  13. * seL4_CapRightsBits added to libsel4. seL4_CapRightsBits is the number of bits
  14. to encode seL4_CapRights.
  15. * `seL4_UserTop` added
  16. - a new constant in libsel4 that contains the first virtual address unavailable to
  17. user level.
  18. * Support added for Aarch64 hypervisor mode (EL2) for Nvidia TX1 and TX2. This is not verified.
  19. ## Upgrade Notes
  20. ---
  21. 10.1.1 2018-11-12: BINARY COMPATIBLE
  22. ## Changes
  23. * Remove theoretical uninitialised variable use in infer_cpu_gic_id for binary translation validation
  24. ## Upgrade Notes
  25. * 10.1.0 has a known broken test in the proofs. 10.1.1 fixes this test.
  26. ---
  27. 10.1.0 2018-11-07: SOURCE COMPATIBLE
  28. ## Changes
  29. * structures in the boot info are not declared 'packed'
  30. - these were previously packed (in the GCC attribute sense)
  31. - some field lengths are tweaked to avoid padding
  32. - this is a source-compatible change
  33. * ARM platforms can now set the trigger of an IRQ Handler capability
  34. - seL4_IRQControl_GetTrigger allows users to obtain an IRQ Handler capability
  35. and set the trigger (edge or level) in the interrupt controller.
  36. * Initial support for NVIDIA Jetson TX2 (ARMv8a, Cortex A57)
  37. * AARCH64 support added for raspberry pi 3 platform.
  38. * Code generation now use jinja2 instead of tempita.
  39. * AARCH32 HYP support added for running multiple ARM VMs
  40. * AARCH32 HYP VCPU registers updated.
  41. * A new invocation for setting TLSBase on all platforms.
  42. - seL4_TCB_SetTLSBase
  43. * Kbuild/Kconfig/Makefile build system removed.
  44. ---
  45. 10.0.0 2018-05-28: BREAKING
  46. - Final version of the kernel which supports integration with Kbuild based projects
  47. - Future versions, including this one, provide a CMake based build system
  48. For more information see
  49. ## Changes
  50. * x86 IO ports now have an explicit IOPortControl capability to gate their creation. IOPort capabilities may now only
  51. be created through the IOPortControl capability that is passed to the rootserver. Additionally IOPort capabilities
  52. may not be derived to have smaller ranges and the IOPortControl will not issue overlapping IOPorts
  53. * 32-bit support added for the initial prototype RISC-V architecture port
  54. ## Upgrade Notes
  55. * A rootserver must now create IOPort capabilities from the provided IOPortControl capability. As IOPorts can not
  56. have their ranges further restricted after creation it must create capabilities with the final desired granularity,
  57. remembering that since ranges cannot overlap you cannot issue a larger and smaller range that have any IO ports
  58. in common.
  59. ---
  60. 9.0.1 2018-04-18: BINARY COMPATIBLE
  61. ## Changes
  62. * On 64-bit architectures, the `label` field of `seL4_MessageInfo` is now 52 bits wide. User-level programs
  63. which use any of the following functions may break, if the program relies on these functions to mask the
  64. `label` field to the previous width of 20 bits.
  65. - `seL4_MessageInfo_new`
  66. - `seL4_MessageInfo_get_label`
  67. - `seL4_MessageInfo_set_label`
  68. * Initial prototype RISC-V architecture port. This port currently only supports running in 64-bit mode without FPU or
  69. or multicore support on the Spike simulation platform. There is *no verification* for this platform.
  70. ## Upgrade Notes
  71. ---
  72. 9.0.0 2018-04-11: BREAKING
  73. = Changes =
  74. * Debugging option on x86 for syscall interface to read/write MSRs (this is an, equally dangerous, alternative to
  75. dangerous code injection)
  76. * Mitigation for Meltdown ( on x86-64 implemented. Mitigation is via a form of kernel
  77. page table isolation through the use of a Static Kernel Image with Microstate (SKIM) window that is used for
  78. trapping to and from the kernel address space. This can be enabled/disabled through the build configuration
  79. depending on whether you are running on vulnerable hardware or not.
  80. * Mitigation for Spectre ( on x86 against the kernel implemented. Default is software
  81. mitigation and is the best performing so users need to do nothing. This does *not* prevent user processes from
  82. exploiting each other.
  83. * x86 configuration option for performing branch prediction barrier on context switch to prevent Spectre style
  84. attacks between user processes using the indirect branch predictor
  85. * x86 configuration option for flushing the RSB on context switch to prevent Spectre style attacks between user
  86. processes using the RSB
  87. * Define extended bootinfo header for the x86 TSC frequency
  88. * x86 TSC frequency exported in extended bootinfo header
  89. * `archInfo` is no longer a member of the bootinfo struct. Its only use was for TSC frequency on x86, which
  90. can now be retrieved through the extended bootinfo
  91. * Invocations to set thread priority and maximum control priority (MCP) have changed.
  92. - For both invocations, users must now provide a TCB capability `auth`
  93. - The requested MCP/priority is checked against the MCP of the `auth` capability.
  94. - Previous behavior checked against the invoked TCB, which could be subject to the confused deputy
  95. problem.
  96. * seL4_TCB_Configure no longer takes prio, mcp as an argument. Instead these fields must be set separately
  97. with seL4_TCB_SetPriority and seL4_TCB_SetMCPriority.
  98. * seL4_TCB_SetPriority and seL4_TCB_SetMCPriority now take seL4_Word instead of seL4_Uint8.
  99. - seL4_MaxPrio remains at 255.
  100. * seL4_TCB_SetSchedParams is a new method where MCP and priority can be set in the same sytsem call.
  101. * Size of the TCB object is increased for some build configurations
  102. = Upgrade notes =
  103. * seL4_TCB_Configure calls that set priority should be changed to explicitly call seL4_TCB_SetSchedParams
  104. or SetPriority
  105. * seL4_TCB_Configure calls that set MCP should be changed to explicitly call seL4_TCB_SetSchedParams
  106. or seL4_TCB_SetMCPriority
  107. ---
  108. 8.0.0 2018-01-17
  109. = Changes =
  110. * Support for additional zynq platform Zynq UltraScale+ MPSoC (Xilinx ZCU102, ARMv8a, Cortex A53)
  111. * Support for multiboot2 bootloaders on x86 (contributed change from Genode Labs)
  112. * Deprecate seL4_CapData_t type and functions related to it
  113. * A fastpath improvement means that when there are two runnable threads and the target thread is the highest priority
  114. in the scheduler, the fastpath will be hit. Previously the fastpath would not be used on IPC from a high priority
  115. thread to a low priority thread.
  116. * As a consequence of the above change, scheduling behaviour has changed in the case where a non-blocking IPC is sent
  117. between two same priority threads: the sender will be scheduled, rather than the destination.
  118. * Benchmarking support for armv8/aarch64 is now available.
  119. * Additional x86 extra bootinfo type for retrieving frame buffer information from multiboot 2
  120. * Debugging option to export x86 Performance-Monitoring Counters to user level
  121. = Upgrade notes =
  122. * seL4_CapData_t should be replaced with just seL4_Word. Construction of badges should just be `x` instead of
  123. `seL4_CapData_Badge_new(x)` and guards should be `seL4_CNode_CapData_new(x, y)` instead of
  124. `seL4_CapData_Guard_new(x, y)`
  125. * Code that relied on non-blocking IPC to switch between threads of the same priority may break.
  126. ---
  127. 7.0.0 2017-09-05
  128. = Changes =
  129. * Support for building standalone ia32 kernel added
  130. * ia32: Set sensible defaults for FS and GS selectors
  131. * aarch64: Use tpidrro_el0 for IPC buffer instead of tpidr_el0
  132. * More seL4 manual documentation added for aarch64 object invocations
  133. * Default NUM_DOMAINS set to 16 for x86-64 standalone builds
  134. * libsel4: Return seL4_Error in invocation stubs in 8fb06eecff9 ''' This is a source code level breaking change '''
  135. * Add a CMake based build system
  136. * x86: Increase TCB size for debug builds
  137. * libsel4: x86: Remove nested struct declarations ''' This is a source code level breaking change '''
  138. * Bugfix: x86: Unmap pages when delete non final frame caps
  139. = Upgrade notes =
  140. * This release is not source compatible with previous releases.
  141. * seL4 invocations that previously returned long now return seL4_Error which is an enum. Our libraries have already
  142. been updated to reflect this change, but in other places where seL4 invocations are used directly, the return types
  143. will need to be updated to reflect this change.
  144. * On x86 some structs in the Bootinfo have been rearranged. This only affects seL4_VBEModeInfoBlock_t which is used if
  145. VESA BIOS Extensions (VBE) information is being used.
  146. = Known issues =
  147. * One of our tests is non-deterministicly becoming unresponsive on the SMP release build on the Sabre IMX.6 platform,
  148. which is a non verified configuration of the kernel. We are working on fixing this problem, and will likely do a
  149. point release once it is fixed.
  150. ---
  151. For previous releases see